Etiqueta de registo: 00230nam 2200025 450
001 1714164
003 http://id.bnportugal.gov.pt/bib/catbnp/1714164
100 ## $a20090527d2007 k y0pory01030103ba
101 0# $aeng$dpor
102 ## $aPT
105 ## $aa m 000yy
106 ## $ar
200 1# $aLAYGEN - automatic layout generation of analog ICs based on hierachical template descriptions and intelligent computing techniques$fNuno Calado Correia Lourenço$gorient. Nuno Cavaco Gomes Horta
210 #9 $aLisboa$c[s.n.],$d2007
215 ## $aXIV, 150 p.$cil.$d30 cm
320 ## $aBibliografia, p. 147-150
328 #0 $bTese mestr.$cEngenharia Electrotécnica e de Computadores$eInst. Superior Técnico, Univ. Técnica de Lisboa$d2007
675 ## $a621.3.04(043)$vBN$zpor$31227036
675 ## $a681.5(043)$vBN$zpor$3297997
675 ## $a004.92(043)$vBN$zpor$31233873
700 #1 $aLourenço,$bNuno Calado Correia$31378004
702 #1 $aHorta,$bNuno Cavaco Gomes,$f1965-$4727$383100
712 02 $aUniversidade Técnica de Lisboa.$bInstituto Superior Técnico$4295$3175770
801 #0 $aPT$bBN$gRPC
966 ## $lBN$mFGMON$sP. 26292 V.$x1

Etiqueta de registo: 00000nam 2200025 450
001 1901945
003 http://id.bnportugal.gov.pt/bib/catbnp/1901945
100 ## $a20150526d2014 k y0pory01030103ba
101 0# $aeng$dpor
102 ## $aPT
105 ## $aa m 000yy
106 ## $ar
200 1# $aAutomatic analog IC sizing and optimization constrained with PVT corners and layout effects$fNuno Calado Correia Lourenço$gsupervisor Nuno Cavaco Gomes Horta
210 #9 $aLisboa$c[s.n.],$d2014
215 ## $aXVII, 140 p.$cil.$d30 cm
320 ## $aBibliografia, p. 133-140
328 #1 $aTese dout. Electrical and Computing Engineering, Instituto Superior Técnico, Univ. de Lisboa, 2014
675 ## $a621.3.04(043)$vBN$zpor$31227036
675 ## $a681.5(043)$vBN$zpor$3297997
675 ## $a004.92(043)$vBN$zpor$31233873
700 #1 $aLourenço,$bNuno Calado Correia$31378004
702 #1 $aHorta,$bNuno Cavaco Gomes,$f1965-$4727$383100
801 #0 $aPT$bBN$gRPC
966 ## $lBN$mFGMON$sS.A. 157685 V.$x1