Etiqueta de registo: 00000nam 2200025 450
001 2037614
003 http://id.bnportugal.gov.pt/bib/catbnp/2037614
100 ## $a20200106d2019 k y0pory01030103ba
101 0# $aeng$dpor
102 ## $aPT
105 ## $aa m 000yy
106 ## $ar
200 1# $aYield-aware analog IC design and optimization in nanometer-scale technologies$fAntónio Manuel Lourenço Canelas$gsupervisor Nuno Cavaco Gomes Horta, Jorge Manuel Correia Guilherme
210 #9 $aLisboa$c[s.n.],$d2019
215 ## $aXXII, 206 p.$cil.$d30 cm
328 #1 $aTese dout. Electrical and Computer Engineering, Instituto Superior Técnico, Universidade de Lisboa, 2019
675 ## $a681.5(043)$vBN$zpor$3297997
675 ## $a004.02(043)$vBN$zpor$31286563
675 ## $a004.72(043)$vBN$zpor$3959974
675 ## $a519.23/24(043)$vBN$zpor$31777254
700 #1 $aCanelas,$bAntónio Manuel Lourenço$31772713
702 #1 $aHorta,$bNuno Cavaco Gomes,$f1965-$4727$383100
702 #1 $aGuilherme,$bJorge Manuel Correia$4727$3169817
801 #0 $aPT$bBN$gRPC
966 ## $lBN$mFGMON$sS.A. 174186 V.$x1